1. Field of the Invention
The present invention generally relates to a log likelihood ratio (LLR) generation method for an error checking and correcting (ECC) procedure, and more particularly, to a memory storage device and a memory controller using the LLR generation method.
2. Description of Related Art
Along with the widespread of digital cameras, cell phones, and MP3 in recently years, the consumers' demand to digital storage media has increased drastically. Flash memory is one of the most adaptable storage media to be carried around and used for storing digital files due to its many characteristics such as data non-volatility, low power consumption, small volume, and non-mechanical structure. A solid state drive (SSD) is a storage device which uses a flash memory as its storage medium, and SSD has been broadly applied in computer systems as the master hard discs.
Existing flash memories can be categorized into NOR flash memories and NAND flash memories. The flash memories can also be categorized into multi-level cell (MLC) flash memories and single-level cell (SLC) flash memories according to the number of data bits stored in each memory cell. Each memory cell of a SLC flash memory stores data of only one bit, while each memory cell of a MLC flash memory stores data of two or more bits. Taking a 4-level cell flash memory as an example, each memory cell thereof stores data of 2 bits (i.e., “11”, “10”, “00”, and “01”).
The memory cells in a flash memory are connected by bit lines and word lines into a memory cell array. When the control circuit for controlling the bit lines and the word lines reads data from or writes data into a specific memory cell of the memory cell array, the floating voltages in other memory cells may be disturbed and accordingly error bits may be produced. Namely, the data read by the control circuit from the memory cell (also referred to as read data) is different from the originally written data (also referred to as write data). Or, when the flash memory is worn out due to long idle time, memory leakage, or repeated erasing or writing operations, the floating voltages in the memory cells may also be altered to produce error bits.
An error checking and correcting (ECC) circuit is usually disposed in a memory storage device for performing an ECC encoding on the write data and an ECC decoding on the read data (also referred to as ECC procedures) to correct any error bit. Due to the process advancement or the hardware structure of the flash memory (for example, the more data bits are stored in each memory cell of a flash memory, the more error bits may be produced), such a memory storage device needs to perform the ECC procedure on data by using an ECC technique with a good ECC performance (for example, with a low density parity check (LDPC) code). A lookup table is stored in a memory storage device for recording a mapping relation between soft information and a probability (referred to as a log likelihood ratio (LLR)) of the soft information being corresponded to 0 or 1. Thus, when a LDPC code is used for performing the ECC procedure, the memory storage device first obtains the soft information from a memory cell and then obtains the LLR of the soft information from the lookup table. Then, the memory storage device performs the ECC operation by using the LDPC code. The value of the LLR recorded in the lookup table can be obtained by writing and reading training samples. An accurate LLR can reduce the iteration times in the ECC procedure performed by using the LDPC code, and accordingly, the time for performing ECC decoding on read data can be shortened. However, the error characteristic of a flash memory in a memory storage device changes along with the increase in the erase-program times of the flash memory. Thus, to achieve an optimal LLR, the error characteristic of the flash memory has to be continuously determined, which brings a heavy load to the system.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.